Subhashish Mitra is leading the team that is researching a way of expanding the capacity of chips. (Picture credit: med.stanford.edu)
Washington:
For decades, the mantra of electronics has been smaller, faster, cheaper. Stanford University engineers, led by an Indian-origin scientist, have added a fourth word - taller.
A team from the US-based university is set to reveal how to build "high-rise" chips that could increase manifold the performance of the single-storey logic and memory chips.
Subhasish Mitra, professor of electrical engineering and computer science, and HS Philip Wong from Stanford's school of engineering are set to describe the new high-rise chip architecture in a paper at the "IEEE International Electron Devices Meeting" in San Francisco this week.
"This research is at an early stage but our design and fabrication techniques are scalable," Mitra said.
"With further development this architecture could lead to computing performance that is much, much greater than anything available today," he added.
The Stanford approach would build layers of logic atop layers of memory to create a tightly interconnected high-rise chip.
Many thousands of nano-scale electronic elevators would move data between the layers much faster, using less electricity.
The prototype chip shows how to put logic and memory together into 3D structures that can be mass-produced.
"With this new architecture, electronics manufacturers could put the power of a supercomputer in your hand," Wong said.
Unlike today's memory chips, this new storage technology is not based on silicon.
Instead, the Stanford team used titanium nitride, hafnium oxide and platinum.
A team from the US-based university is set to reveal how to build "high-rise" chips that could increase manifold the performance of the single-storey logic and memory chips.
Subhasish Mitra, professor of electrical engineering and computer science, and HS Philip Wong from Stanford's school of engineering are set to describe the new high-rise chip architecture in a paper at the "IEEE International Electron Devices Meeting" in San Francisco this week.
"This research is at an early stage but our design and fabrication techniques are scalable," Mitra said.
"With further development this architecture could lead to computing performance that is much, much greater than anything available today," he added.
The Stanford approach would build layers of logic atop layers of memory to create a tightly interconnected high-rise chip.
Many thousands of nano-scale electronic elevators would move data between the layers much faster, using less electricity.
The prototype chip shows how to put logic and memory together into 3D structures that can be mass-produced.
"With this new architecture, electronics manufacturers could put the power of a supercomputer in your hand," Wong said.
Unlike today's memory chips, this new storage technology is not based on silicon.
Instead, the Stanford team used titanium nitride, hafnium oxide and platinum.
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